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RFD20N03, RFD20N03SM
Data Sheet July 1999 File Number
4350.1
20A, 30V, 0.025 Ohm, N-Channel Power MOSFETs
The RFD20N03 and RFD20N03SM N-Channel power MOSFETs are manufactured using the MegaFET process. This process which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49235.
Features
* 20A, 30V * rDS(ON) = 0.025 * Temperature Compensating PSPICE(R) Model * Thermal Impedance SPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFD20N03 RFD20N03SM PACKAGE TO-251AA TO-252AA BRAND F20N03 F20N03
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, e.g., RFD20N03SM9A.
G
S
Packaging
JEDEC TO-251AA JEDEC TO-252AA
DRAIN (FLANGE)
SOURCE DRAIN GATE GATE SOURCE
DRAIN (FLANGE)
4-427
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFD20N03, RFD20N03SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified 30 30 20 20 Figure 5 Figure 6 90 0.60 -55 to 175 300 260 UNITS V V V A
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation (Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC (Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 11) VGS = VDS, ID = 250A (Figure 10) VDS = 30V, VGS = 0V VDS = 30V, VGS = 0V, TC = 150oC MIN 30 2 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 15V, ID 20A, RL = 0.75 Ig(REF) = 1.0mA (Figure 13) (Figure 3) TO-251, TO-252 TYP 0.022 10 30 12 32 60 28 2.4 1150 550 110 MAX 4 1 50 100 0.025 60 66 75 40 2.9 1.66 100 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJC RJA
VGS = 20V ID = 20A, VGS = 10V (Figure 9) VDD = 15V, ID 20A, RL =0.75, VGS = 10V, RGS = 9.1
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = 20A ISD = 20A, dISD/dt = 100A/s ISD = 20A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 70 145 UNITS V ns nC
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RFD20N03, RFD20N03SM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175 ID, DRAIN CURRENT (A) 25
20
15
10
5
0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-2 10-3 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101
0.01 10-5
10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TJ = MAX RATED TC = 25oC IDM, PEAK CURRENT (A)
500 VGS = 20V
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
ID, DRAIN CURRENT (A)
100 100s
= I25
175 - TC 150
100
VGS = 10V
1ms 10 10ms 100ms DC VDSS(MAX) = 30V 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
10 10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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RFD20N03, RFD20N03SM Typical Performance Curves
300 IAS, AVALANCHE CURRENT (A)
(Continued)
100 VGS = 20V VGS = 10V ID, DRAIN CURRENT (A) 80
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) + 1]
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 7V
100
60
STARTING TJ = 25oC
40
VGS = 6V
STARTING TJ = 150oC 10 0.001
20
VGS = 5V
1 0.01 0.1 tAV, TIME IN AVALANCHE (ms)
10
0
0
1
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
100 ID(ON), ON-STATE DRAIN CURRENT (A) 2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 25oC
FIGURE 7. SATURATION CHARACTERISTICS
80
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
-55oC
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 20A
175oC 60
1.5
40
1.0
20
0 0 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V)
0.5 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE
1.2
ID = 250A
1.0
1.1
0.8
1.0
0.6
0.9
0.4 -80
-40
0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
0.8 -80
-40
0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
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RFD20N03, RFD20N03SM Typical Performance Curves
1800
VGS , GATE TO SOURCE VOLTAGE (V)
(Continued)
10
1500
C, CAPACITANCE (pF)
CISS 1200 900 COSS 600 CRSS 300 0 0 10 20
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
VDD = 15V
8
6
4
2
WAVEFORMS IN DESCENDING ORDER: ID = 20A ID = 15A ID = 10A ID = 5A 0 6 12 18 Qg, GATE CHARGE (nC) 24 30
30
0
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V
DUT Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
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RFD20N03, RFD20N03SM Test Circuits and Waveforms
(Continued)
VDS
tON td(ON) RL tr VDS 90%
tOFF td(OFF) tf 90%
VGS
+
DUT RGS
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
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RFD20N03, RFD20N03SM PSPICE Electrical Model
SUBCKT RFD20N03, RFD20N03SM 2 1 3 ;
CA 12 8 1.3e-9 CB 15 14 1.3e-9 CIN 6 8 9.9e-10
LDRAIN
rev 28 Jul 97
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 33.15 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1.00e-9 LGATE 1 9 3.57e-9 LSOURCE 3 7 4.25e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5e-4 RGATE 9 20 1.24 RLDRAIN 2 5 10 RLGATE 1 9 28.6 RLSOURCE 3 7 26.9 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 6.2e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 S1B CA 13 8 GATE 1 RLGATE
DPLCAP 10
5 RLDRAIN DBREAK 11 + 17 EBREAK 18
DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S2A 14 13 S2B 15 17 RBREAK 18 RVTEMP CB + 6 8 EDS 5 8 14 IT 19 7 SOURCE 3
13 + EGS
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),3))} .MODEL DBODYMOD D (IS = 9e-13 RS = 6.4e-3 IKF=7.4 TIKF=0.005 N=1.02 TRS1 = 3.5e-3 TRS2 =-1e-5 CJO = 1.78e-9 TT = 4.0e-8 M = 0.4053) .MODEL DBREAKMOD D (RS = 0.1 N=3.5 IKF=-1e-3 TRS1 = -1e-3 TRS2 =1e-6) .MODEL DPLCAPMOD D (CJO = 1.3e-9 IS = 1e-30 N = 10 M = 0.62) .MODEL MMEDMOD NMOS (VTO = 3.17 KP = 1.3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.24) .MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.68 KP = 0.009 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 12.4 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 8e-4 TC2 = 4.5e-7) .MODEL RDRAINMOD RES (TC1 = 3.5e-2 TC2 = 4.5e-4) .MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -1.2e-3 TC2 = -2e-5) .MODEL RVTEMPMOD RES (TC1 = -3.5e-3 TC2 = 1e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -8.60 VOFF= -2.50) VON = -2.50 VOFF= -8.60) VON = 0.00 VOFF= 0.30) VON = 0.30 VOFF= 0.00)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
4-433
+
-
RDRAIN 21 16
DBODY
MWEAK MMED
VBAT +
8 22 RVTHRES
RFD20N03, RFD20N03SM SPICE Thermal Model
REV 28 July 97 RFD20N03, RFD20N03SM CTHERM1 7 6 9.9e-7 CTHERM2 6 5 1.5e-3 CTHERM3 5 4 2.2e-3 CTHERM4 4 3 5.7e-3 CTHERM5 3 2 7.5e-2 CTHERM6 2 1 5.4e-1 RTHERM1 7 6 8e-3 RTHERM2 6 5 2.3e-2 RTHERM3 5 4 9.0e-2 RTHERM4 4 3 6.9e-1 RTHERM5 3 2 6.1e-1 RTHERM6 2 1 8.0e-2
7 JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
CASE
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